| 2008 |
|---|
| 6 | EE | Hidehiro Toyoda,
Michitaka Okuno,
Shinji Nishimura,
Matsuaki Terada:
A 100 Gb/s and High-Reliable Physical-Layer Architecture for VSR and Backplane Ethernet.
ICC 2008: 5417-5421 |
| 2007 |
|---|
| 5 | EE | Hidehiro Toyoda,
Shinji Nishimura,
Michitaka Okuno,
Matsuaki Terada:
A 100-Gb/s-Physical-Layer Architecture for Higher-Speed Ethernet for VSR and Backplane Applications.
IEICE Transactions 90-C(10): 1957-1963 (2007) |
| 2006 |
|---|
| 4 | EE | Hidehiro Toyoda,
Shinji Nishimura,
Michitaka Okuno,
Kouji Fukuda,
Kouji Nakahara,
Hiroaki Nishi:
100-Gb/s Physical-Layer Architecture for Next-Generation Ethernet.
IEICE Transactions 89-B(3): 696-703 (2006) |
| 3 | EE | Michitaka Okuno,
Shinji Nishimura,
Shin-ichi Ishida,
Hiroaki Nishi:
Cache-Based Network Processor Architecture: Evaluation with Real Network Traffic.
IEICE Transactions 89-C(11): 1620-1628 (2006) |
| 2005 |
|---|
| 2 | EE | Michitaka Okuno,
Shin-ichi Ishida,
Hiroaki Nishi:
Low-Power Network-Packet-Processing Architecture Using Process-Learning Cache for High-End Backbone Router.
IEICE Transactions 88-C(4): 536-543 (2005) |
| 1996 |
|---|
| 1 | | Keisuke Inoue,
Toru Kisuki,
Michitaka Okuno,
Etsuko Shimizu,
Takuya Terasawa,
Hideharu Amano:
ATTEMPT-1: A Reconfigurable Multiprocessor Testbed.
FPL 1996: 200-209 |
