| |
| 2006 | ||
|---|---|---|
| 3 | EE | Takanori Komuro, Naoto Hayasaka, Haruo Kobayashi, Hiroshi Sakayori: A Practical Analog BIST Cooperated with an LSI Tester. IEICE Transactions 89-A(2): 465-468 (2006) |
| 2005 | ||
| 2 | EE | Takanori Komuro, Naoto Hayasaka, Haruo Kobayashi, Hiroshi Sakayori: A practical BIST circuit for analog portion in deep sub-micron CMOS system LSI. ISCAS (5) 2005: 4281-4284 |
| 1995 | ||
| 1 | Haruo Kobayashi, Hiroshi Sakayori, Tsutomu Tobari, Hiroyuki Matsuura: Error Correction Algorithm for Folding/Interpolation ADC. ISCAS 1995: 700-703 | |
| 1 | Naoto Hayasaka | [2] [3] |
| 2 | Haruo Kobayashi | [1] [2] [3] |
| 3 | Takanori Komuro | [2] [3] |
| 4 | Hiroyuki Matsuura | [1] |
| 5 | Tsutomu Tobari | [1] |