2008 |
25 | EE | Imran Rafiq Quadri,
Pierre Boulet,
Samy Meftali,
Jean-Luc Dekeyser:
Using an MDE Approach for Modeling of Interconnection Networks.
ISPAN 2008: 289-294 |
24 | EE | Abdoulaye Gamatié,
Éric Rutten,
Huafeng Yu,
Pierre Boulet,
Jean-Luc Dekeyser:
Modeling and Formal Validation of High-Performance Embedded Systems.
ISPDC 2008: 215-222 |
23 | EE | Calin Glitia,
Pierre Boulet:
High Level Loop Transformations for Systematic Signal Processing Embedded Applications.
SAMOS 2008: 187-196 |
2007 |
22 | EE | Pierre Boulet,
Philippe Marquet,
Éric Piel,
Julien Taillard:
Repetitive Allocation Modelling with MARTE.
FDL 2007: 280-285 |
2006 |
21 | EE | Ouassila Labbani,
Éric Rutten,
Jean-Luc Dekeyser,
Pierre Boulet:
UML2 Profile for Modeling Controlled Data Parallel Applications.
FDL 2006: 359-367 |
2005 |
20 | EE | Lossan Bonde,
Pierre Boulet,
Jean-Luc Dekeyser:
Traceability and Interoperability in Models Transformations.
FDL 2005: 543-555 |
19 | EE | Ouassila Labbani,
Jean-Luc Dekeyser,
Pierre Boulet:
Mode-Automata Based Methodology for Scade.
HSCC 2005: 386-401 |
18 | EE | Abdelkader Amar,
Pierre Boulet,
Philippe Dumont:
Projection of the Array-OL Specification Language onto the Kahn Process Network Computation Model.
ISPAN 2005: 496-503 |
17 | EE | Arnaud Cuccuru,
Jean-Luc Dekeyser,
Philippe Marquet,
Pierre Boulet:
Towards UML 2 Extensions for Compact Modeling of Regular Complex Topologies.
MoDELS 2005: 445-459 |
16 | EE | Ashish Meena,
Pierre Boulet:
Model Driven Scheduling Framework for Multiprocessor SoC Design.
PPAM 2005: 888-895 |
15 | | Pierre Boulet,
Arnaud Cuccuru,
Jean-Luc Dekeyser,
Ashish Meena:
Model Driven Engineering for Regular MPSoC Co-design.
ReCoSoC 2005: 129-136 |
2004 |
14 | EE | Arnaud Cuccuru,
Pierre Boulet,
Jean-Luc Dekeyser:
Regular Hardware Architecture Modeling with UML2.
FDL 2004: 289-301 |
2003 |
13 | EE | Pierre Boulet,
Jean-Luc Dekeyser,
Cédric Dumoulin,
Philippe Marquet:
MDA for SoC Design, Intensive Signal Processing Experiment.
FDL 2003: 309-317 |
12 | | Abdelkader Amar,
Pierre Boulet,
Jean-Luc Dekeyser,
T. Theeuwen:
Distributed Process Networks - Using Half FIFO Queues in CORBA.
PARCO 2003: 31-38 |
2002 |
11 | EE | Florent Devin,
Pierre Boulet,
Jean-Luc Dekeyser,
Philippe Marquet:
GASPARD - A Visual Parallel Programming Environment.
PARELEC 2002: 145-150 |
2000 |
10 | EE | Emmanuel Cagniot,
Jean-Luc Dekeyser,
Pierre Boulet,
Thomas Brandes,
Francis Piriou,
Georges Marques:
Parallelization of a 3D Magnetostatic Code Using High Performance Fortran.
PARELEC 2000: 181-185 |
9 | EE | Emmanuel Cagniot,
Thomas Brandes,
Jean-Luc Dekeyser,
Francis Piriou,
Pierre Boulet,
Stéphane Clénet:
High Level Parallelization of a 3D Electromagnetic Simulation Code with Irregular Communication Patterns.
VECPAR 2000: 519-528 |
1999 |
8 | | Pierre Boulet,
Jack Dongarra,
Yves Robert,
Frédéric Vivien:
Static tiling for heterogeneous computing platforms.
Parallel Computing 25(5): 547-568 (1999) |
7 | | Pierre Boulet,
Jack Dongarra,
Fabrice Rastello,
Yves Robert,
Frédéric Vivien:
Algorithmic Issues on Heterogeneous Computing Platforms.
Parallel Processing Letters 9(2): 197-213 (1999) |
1998 |
6 | EE | Pierre Boulet,
Xavier Redon:
Communication Pre-evaluation in HPF.
Euro-Par 1998: 263-272 |
5 | EE | Pierre Boulet,
Paul Feautrier:
Scanning Polyhedra without Do-loops.
IEEE PACT 1998: 4-11 |
4 | | Pierre Boulet,
Alain Darte,
Georges-André Silber,
Frédéric Vivien:
Loop Parallelization Algorithms: From Parallelism Extraction to Code Generation.
Parallel Computing 24(3-4): 421-444 (1998) |
1996 |
3 | | Pierre Boulet,
Thomas Brandes:
Evaluation of Automatic Parallelization Strategies for HPF Compilers.
HPCN Europe 1996: 778-783 |
2 | | Pierre Boulet:
Bouclettes: A Fortran Loop Parallelizer.
HPCN Europe 1996: 784-791 |
1994 |
1 | | Vincent Bouchitté,
Pierre Boulet,
Alain Darte,
Yves Robert:
Evaluating Array Expressions on Massively Parallel Machines with Communication/ Computation Overlap.
CONPAR 1994: 713-724 |