| 2005 |
|---|
| 4 | EE | Akira Yamazaki,
Fukashi Morishita,
Naoya Watanabe,
Teruhiko Amano,
Masaru Haraguchi,
Hideyuki Noda,
Atsushi Hachisuka,
Katsumi Dosaka,
Kazutami Arimoto,
Setsuo Wake,
Hideyuki Ozaki,
Tsutomu Yoshihara:
A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM Macros.
IEICE Transactions 88-C(10): 2020-2027 (2005) |
| 1991 |
|---|
| 3 | | Jaime Jungok Bae,
Tatsuya Suda,
Naoya Watanabe:
Evaluation of the Effects of Protocol Processing Overhead in Error Recovery Schemes for a High-Speed Packet Switched Network: Link-by-Link versus Edge-to-Edge Schemes.
IEEE Journal on Selected Areas in Communications 9(9): 1496-1509 (1991) |
| 1986 |
|---|
| 2 | | Naoya Watanabe,
Ken-ichi Yukimatsu,
Toshiaki Doi,
Masachika Ishizura,
Etsugo Yoneda,
Makoto Kawashima,
Kazuhiro Hayashi:
Network Testing for Digital Data Networks.
ICC 1986: 588-592 |
| 1 | | Ken-ichi Yukimatsu,
Naoya Watanabe,
Takashi Honda:
Multicast Communication Facilities in a High Speed Packet Switching Network.
ICCC 1986: 276-281 |
