| |
| 2008 | ||
|---|---|---|
| 6 | EE | Zhiqiang Cui, Zhongfeng Wang: Extended layered decoding of LDPC codes. ACM Great Lakes Symposium on VLSI 2008: 457-462 |
| 2007 | ||
| 5 | EE | Zhiqiang Cui, Zhongfeng Wang: Efficient Message Passing Architecture for High Throughput LDPC Decoder. ISCAS 2007: 917-920 |
| 4 | EE | Zhongfeng Wang, Zhiqiang Cui: Low-Complexity High-Speed Decoder Design for Quasi-Cyclic LDPC Codes. IEEE Trans. VLSI Syst. 15(1): 104-114 (2007) |
| 3 | EE | Zhongfeng Wang, Zhiqiang Cui: A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes. IEEE Trans. VLSI Syst. 15(4): 483-488 (2007) |
| 2006 | ||
| 2 | EE | Zhiqiang Cui, Zhongfeng Wang: A 170 Mbps (8176, 7156) quasi-cyclic LDPC decoder implementation with FPGA. ISCAS 2006 |
| 1 | EE | Zhiqiang Cui, Zhongfeng Wang: Area-efficient parallel decoder architecture for high rate QC-LDPC codes. ISCAS 2006 |
| 1 | Zhongfeng Wang | [1] [2] [3] [4] [5] [6] |