| 2007 |
|---|
| 5 | EE | Venkat Satagopan,
Bonita Bhaskaran,
Waleed Al-Assadi,
Scott C. Smith,
Sindhu Kakarla:
DFT Techniques and Automation for Asynchronous NULL Conventional Logic Circuits.
IEEE Trans. VLSI Syst. 15(10): 1155-1159 (2007) |
| 4 | EE | Venkat Satagopan,
Bonita Bhaskaran,
Anshul Singh,
Scott C. Smith:
Automated energy calculation and estimation for delay-insensitive digital circuits.
Microelectronics Journal 38(10-11): 1095-1107 (2007) |
| 2005 |
|---|
| 3 | | Waleed Al-Assadi,
Pavankumar Chandrasekhar,
Bonita Bhaskaran:
Fault Modeling and Testability of CMOS Domino Circuits.
CDES 2005: 21-27 |
| 2 | | Bonita Bhaskaran,
Venkat Satagopan,
Scott C. Smith:
High-Speed Energy Estimation for Delay-Insensitive Circuits.
CDES 2005: 35-41 |
| 1 | | Bonita Bhaskaran,
Venkat Satagopan,
Waleed Al-Assadi,
Scott C. Smith:
Implementation of Design For Test for Asynchronous NCL Designs.
CDES 2005: 78-84 |
