| 2009 | 
| 10 | EE | Alexandre Graell i Amat,
Eirik Rosnes:
Good Concatenated Code Ensembles for the Binary Erasure Channel
CoRR abs/0904.2482:  (2009) | 
| 2007 | 
| 9 | EE | Alexandre Graell i Amat,
Raphaël Le Bidan:
Rate-Compatible Serially Concatenated Codes with Outer Extended BCH Codes.
GLOBECOM 2007: 1476-1481 | 
| 8 | EE | Alexandre Graell i Amat,
Alberto Tarable:
On the Design of Space-Time Trellis Codes for Transmit-Correlated Fading Channels.
IEEE Transactions on Communications 55(1): 112-121 (2007) | 
| 2006 | 
| 7 | EE | Alexandre Graell i Amat,
Daniele Vogrig,
Sergio Benedetto,
Guido Montorsi,
Andrea Neviani,
Andrea Gerosa:
Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code.
GLOBECOM 2006 | 
| 6 | EE | Alexandre Graell i Amat,
Fredrik Brannstrom,
Lars K. Rasmussen:
Design of Rate-Compatible Serially Concatenated Convolutional Codes
CoRR abs/cs/0601067:  (2006) | 
| 5 | EE | Alexandre Graell i Amat,
Sergio Benedetto,
Guido Montorsi,
Daniele Vogrig,
Andrea Neviani,
Andrea Gerosa:
Design, Simulation, and Testing of a CMOS Analog Decoder for the Block Length-40 UMTS Turbo Code.
IEEE Transactions on Communications 54(11): 1973-1982 (2006) | 
| 4 | EE | Alexandre Graell i Amat,
Sergio Benedetto,
Guido Montorsi,
Daniele Vogrig,
Andrea Neviani,
Andrea Gerosa:
Design, Simulation, and Testing of a CMOS Analog Decoder for the Block Length-40 UMTS Turbo Code.
IEEE Transactions on Communications 54(6): 1143 (2006) | 
| 2005 | 
| 3 | EE | Alexandre Graell i Amat,
Guido Montorsi,
Francesca Vatta:
Design and Performance Analysis of a New Class of Rate Compatible Serial Concatenated Convolutional Codes
CoRR abs/cs/0510035:  (2005) | 
| 2004 | 
| 2 |   | Alexandre Graell i Amat,
Guido Montorsi,
Sergio Benedetto:
Design and decoding of optimal high-rate convolutional codes.
IEEE Transactions on Information Theory 50(5): 867-881 (2004) | 
| 2002 | 
| 1 | EE | Andrea Xotta,
Daniele Vogrig,
Andrea Gerosa,
Andrea Neviani,
Alexandre Graell i Amat,
Guido Montorsi,
M. Bruccoleri,
G. Betti:
An all-analog CMOS implementation of a turbo decoder for hard-disk drive read channels.
ISCAS (5) 2002: 69-72 |