| 2009 |
|---|
| 8 | EE | Kiyoshi Nagata,
Fidel R. Nemenzo,
Hideo Wada:
The number of self-dual codes over Zp3{Z_{p^3}}.
Des. Codes Cryptography 50(3): 291-303 (2009) |
| 1997 |
|---|
| 7 | EE | Hiroaki Fujii,
Yoshiko Yasuda,
Hideya Akashi,
Yasuhiro Inagami,
Makoto Koga,
Osamu Ishihara,
Masamori Kashiyama,
Hideo Wada,
Tsutomu Sumimoto:
Architecture and Performance of the Hitachi SR2201 Massively Parallel Processor System.
IPPS 1997: 233-241 |
| 6 | EE | Yoshiko Yasuda,
Hiroaki Fujii,
Hideya Akashi,
Yasuhiro Inagami,
Teruo Tanaka,
Junji Nakagoshi,
Hideo Wada,
Tsutomu Sumimoto:
Deadlock-Free Fault-tolerant Routing in the Multi-dimensional Crossbar Network and Its Implementation for the Hitachi SR2201.
IPPS 1997: 346-352 |
| 1993 |
|---|
| 5 | EE | Hiroshi Nakamura,
Taisuke Boku,
Hideo Wada,
Hiromitsu Imori,
Ikuo Nakata,
Yasuhiro Inagami,
Kisaburo Nakazawa,
Yoshiyuki Yamashita:
A Scalar Architecture for Pseudo Vector Processing Based on Slide-Windowed Registers.
International Conference on Supercomputing 1993: 298-307 |
| 1989 |
|---|
| 4 | EE | Hideo Wada,
Tadaaki Isobe,
Masao Furukawa,
Shun Kawabe:
High-speed storage control schemes of HITACHI supercomputer S-820 system.
ICS 1989: 341-350 |
| 3 | | Michihiro Hirai,
Shun Kawabe,
Hideo Wada:
An Overview of the HITACHI S-820 Supercomputer System.
Supercomputer 1989: 56-80 |
| 1988 |
|---|
| 2 | | Hideo Wada,
Koichi Ishii,
Shigeko Yazawa,
Shun Kawabe:
High-Speed Vector Instruction Execution Schemes of HITACHI Supercomputer S-820 System.
ICPP (1) 1988: 291-298 |
| 1 | EE | Hideo Wada,
K. Ishil,
Masakazu Fukagawa,
H. Murayama,
Shun Kawabe:
High-speed processing schemes for summation type and iteration type vector instructions on Hitachi supercomputer S-820 system.
ICS 1988: 196-206 |
