2007 | ||
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1 | EE | Noriaki Oda, Hironori Imura, Naoyoshi Kawahara, Masayoshi Tagami, Hiroyuki Kunishima, Shuji Sone, Sadayuki Ohnishi, Kenta Yamada, Yumi Kakuhara, Makoto Sekine, Yoshihiro Hayashi, Kazuyoshi Ueno: Chip-Level Performance Maximization Using ASIS (Application-Specific Interconnect Structure) Wiring Design Concept for 45 nm CMOS Generation. IEICE Transactions 90-C(4): 848-855 (2007) |
1 | Yoshihiro Hayashi | [1] |
2 | Hironori Imura | [1] |
3 | Yumi Kakuhara | [1] |
4 | Naoyoshi Kawahara | [1] |
5 | Hiroyuki Kunishima | [1] |
6 | Noriaki Oda | [1] |
7 | Sadayuki Ohnishi | [1] |
8 | Makoto Sekine | [1] |
9 | Masayoshi Tagami | [1] |
10 | Kazuyoshi Ueno | [1] |
11 | Kenta Yamada | [1] |