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Ajith Amerasekera

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2007
2EEAjith Amerasekera: Concurrent Optimization of Technology and Design for Nano CMOS. VLSI Design 2007: 27
2002
1EEPrasun Raha, Scott Randall, Richard Jennings, Bob Helmick, Ajith Amerasekera, Baher Haroun: A Robust Digital Delay Line Architecture in a 0.13µm CMOS Technology Node for Reduced Design and Process Sensitivities. ISQED 2002: 148-

Coauthor Index

1Baher Haroun [1]
2Bob Helmick [1]
3Richard Jennings [1]
4Prasun Raha [1]
5Scott Randall [1]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)