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| 1999 | ||
|---|---|---|
| 2 | EE | Lun Ye, Foong-Charn Chang, Peter Feldmann, Rakesh Chadha, Nagaraj Ns, Frank Cano: Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs. DATE 1999: 658-663 |
| 1988 | ||
| 1 | EE | Foong-Charn Chang, Chin-Fu Chen, Prasad Subramaniam: An Accurate and Efficient Gate Level Delay Calculator for MOS Circuits. DAC 1988: 282-287 |
| 1 | Frank Cano | [2] |
| 2 | Rakesh Chadha | [2] |
| 3 | Chin-Fu Chen | [1] |
| 4 | Peter Feldmann | [2] |
| 5 | Nagaraj Ns | [2] |
| 6 | Prasad Subramaniam | [1] |
| 7 | Lun Ye | [2] |