| 2009 |
|---|
| 13 | EE | Keisuke Takemori,
Masahiko Fujinaga,
Toshiya Sayama,
Masakatsu Nishigaki:
Host-based traceback; tracking bot and C&C server.
ICUIMC 2009: 400-405 |
| 2008 |
|---|
| 12 | EE | Takumi Yamamoto,
Atsushi Harada,
Takeo Isarida,
Masakatsu Nishigaki:
Improvement of User Authentication Using Schema of Visual Memory: Exploitation of "Schema of Story".
AINA 2008: 40-47 |
| 11 | EE | Keisuke Takemori,
Masakatsu Nishigaki,
Tomohiro Takami,
Yutaka Miyake:
Detection of Bot Infected PCs Using Destination-Based IP and Domain Whitelists During a Non-Operating Term.
GLOBECOM 2008: 2072-2077 |
| 10 | EE | Hiroaki Kikuchi,
Kei Nagai,
Wakaha Ogata,
Masakatsu Nishigaki:
Privacy-Preserving Similarity Evaluation and Application to Remote Biometrics Authentication.
MDAI 2008: 3-14 |
| 9 | | Masakatsu Nishigaki,
Yoichi Shibata:
Physical Access Control with Biometric Keys.
Security and Management 2008: 213-219 |
| 2007 |
|---|
| 8 | EE | Kei Nagai,
Hiroaki Kikuchi,
Wakaha Ogata,
Masakatsu Nishigaki:
ZeroBio - Evaluation and Development of Asymmetric Fingerprint Authentication System Using Oblivious Neural Network Evaluation Protocol.
ARES 2007: 1155-1159 |
| 7 | | Yoichi Shibata,
Masahiro Mimura,
Kenta Takahashi,
Masakatsu Nishigaki:
A study on biometric key generation from fingerprints: Fingerprint-key generation from stable feature value.
Security and Management 2007: 45-51 |
| 6 | | Takumi Yamamoto,
Atsushi Harada,
Takeo Isarida,
Masakatsu Nishigaki:
Improvement of User Authentication Using Schema of Visual Memory: Guidance by Verbal Cue.
Security and Management 2007: 58-64 |
| 2006 |
|---|
| 5 | EE | Atsushi Harada,
Takeo Isarida,
Tadanori Mizuno,
Masakatsu Nishigaki:
A User Authentication System Using Schema of Visual Memory.
BioADIT 2006: 338-345 |
| 4 | | Yoichi Shibata,
Masahiro Mimura,
Kenta Takahashi,
Masakatsu Nishigaki:
Mechanism-Based PKI - A Real-Time Key Generation from Fingerprints.
Security and Management 2006: 468-474 |
| 2003 |
|---|
| 3 | EE | Masakatsu Nishigaki,
Makoto Nakano,
Masakazu Soga:
A fault-tolerant combinational circuit with fault diagnosis capability - To mask and detect the loss of any one connection between gate circuits.
Systems and Computers in Japan 34(11): 67-80 (2003) |
| 1994 |
|---|
| 2 | | Masaki Ishida,
Koichi Hayashi,
Masakatsu Nishigaki,
Hideki Asai:
Iterated Timing Analysis with Dynamic Partitioning Technique for Bipolar Transistor Circuits.
ISCAS 1994: 411-414 |
| 1 | | Masakatsu Nishigaki,
Nobuyuki Tanaka,
Hideki Asai:
Mixed Mode Circuit Simulator SPLIT2.1 using Dynamic Network Separation and Selective Trace.
ISCAS 1994: 9-12 |
