Seng-Pan U.

2008
24	EE	He Gong Wei, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins: A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier. ISCAS 2008: 5-8
2007
23	EE	Weng-leng Mok, Pui-In Mak, Seng-Pan U., Rui Paulo Martins: A Highly-Linear Successive-Approximation Front-End Digitizer with Built-in Sample-and-Hold Function for Pipeline/Two-Step ADC. ISCAS 2007: 1947-1950
2006
22	EE	Ka-Hou Ao Ieong, Seng-Pan U., Rui Paulo Martins: A 1-V 2.5-mW Transient-Improved Current-Steering DAC using Charge-Removal-Replacement Technique. APCCAS 2006: 183-186
21	EE	Kin-Sang Chio, Seng-Pan U., Rui Paulo Martins: A dual-mode low-distortion sigma-delta modulator with relaxing comparator accuracy. ISCAS 2006
20	EE	Chon-In Lao, Seng-Pan U., Rui Paulo Martins: A novel effective bandpass semi-MASH sigma-delta modulator with double-sampling mismatch-free resonator. ISCAS 2006
19	EE	Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins: A novel low-voltage finite-gain compensation technique for high-speed reset- and switched-opamp circuits. ISCAS 2006
18	EE	Jun-Xia Ma, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins: A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applications. ISCAS 2006
17	EE	Pui-In Mak, Seng-Pan U., Rui Paulo Martins: Design and test strategy underlying a low-voltage analog-baseband IC for 802.11a/b/g WLAN SiP receivers. ISCAS 2006
2005
16	EE	Ka-Hou Ao Ieong, Chong-Yin Fok, Pui-In Mak, Seng-Pan U., Rui Paulo Martins: A frequency up-conversion and two-step channel selection embedded CMOS D/A interface. ISCAS (1) 2005: 392-395
15	EE	Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins: A novel very low-voltage SC-CMFB technique for fully-differential reset-opamp circuits. ISCAS (2) 2005: 1581-1584
14	EE	Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins: A novel low-voltage cross-coupled passive sampling branch for reset- and switched-opamp circuits. ISCAS (2) 2005: 1585-1588
13	EE	Chon-In Lao, Seng-Pan U., Rui Paulo Martins: A novel semi-MASH sub-stage for high-order cascade sigma-delta modulators. ISCAS (4) 2005: 3095-3098
12	EE	Kin-Sang Chio, Seng-Pan U., Rui Paulo Martins: A robust 3rd order low-distortion multi-bit sigma-delta modulator with reduced number of op-amps for WCDMA. ISCAS (4) 2005: 3099-3102
2004
11		Pui-In Mak, Kin-Kwan Ma, Weng-leng Mok, Chi-sam Sou, Kit-man Ho, Cheng-Man Ng, Seng-Pan U., Rui Paulo Martins: An I/Q-multiplexed and OTA-shared CMOS pipelined ADC with an A-DQS S/H front-end for two-step-channel-select low-IF receiver. ISCAS (1) 2004: 1068-1071
10		Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins: A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems. ISCAS (1) 2004: 369-372
9		Pui-In Mak, Seng-Pan U., Rui Paulo Martins: A low-IF/zero-IF reconfigurable receiver with two-step channel selection technique for multistandard applications. ISCAS (4) 2004: 417-420
8		Pui-In Mak, Man-Chung Wong, Seng-Pan U.: A 3D PWM control, H-bridge tri-level inverter for power quality compensation in three-phase four-wired systems. ISCAS (5) 2004: 948-951
2003
7	EE	Chon-In Lao, Ho-leng Leong, Kuoi-Fok Au, Kuok-Hang Mok, Seng-Pan U., Rui Paulo Martins: A 10.7-MHz bandpass sigma-delta modulator using double-delay single-opamp SC resonator with double-sampling. ISCAS (1) 2003: 1061-1064
6	EE	Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, José E. Franca: Timing-mismatch analysis in high-speed analog front-end with nonuniformly holding output. ISCAS (1) 2003: 129-132
2002
5	EE	Seng-Pan U., Rui Paulo Martins, José E. Franca: Design and analysis of low timing-skew clock generation for time-interleaved sampled-data systems. ISCAS (4) 2002: 441-444
2001
4	EE	Seng-Pan U., Rui Paulo Martins, José E. Franca: High-frequency low-power multirate SC realizations for NTSC/PAL digital video filtering. ISCAS (1) 2001: 204-207
3	EE	Seng-Pan U., Rui Paulo Martins, José E. Franca: A high-speed frequency up-translated SC bandpass filter with auto-zeroing for DDFS systems. ISCAS (1) 2001: 320-323
1999
2	EE	Seng-Pan U., Rui Paulo Martins, José E. Franca: Highly accurate mismatch-free SC delay circuits with reduced finite gain and offset sensitivity. ISCAS (2) 1999: 57-60
1	EE	Seng-Pan U., Rui Paulo Martins, José E. Franca: High performance multirate SC circuits with predictive correlated double sampling technique. ISCAS (2) 1999: 77-80

Coauthor Index

1	Kuoi-Fok Au	[7]
2	Kin-Sang Chio	[12] [21]
3	U. Fat Chio	[24]
4	Chong-Yin Fok	[16]
5	José E. Franca	[1] [2] [3] [4] [5] [6]
6	Kit-man Ho	[11]
7	Ka-Hou Ao Ieong	[16] [22]
8	Chon-In Lao	[7] [13] [20]
9	Ho-leng Leong	[7]
10	Jun-Xia Ma	[18]
11	Kin-Kwan Ma	[11]
12	Pui-In Mak	[8] [9] [11] [16] [17] [23]
13	Rui Paulo Martins	[1] [2] [3] [4] [5] [6] [7] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24]
14	Kuok-Hang Mok	[7]
15	Weng-leng Mok	[11] [23]
16	Cheng-Man Ng	[11]
17	Sai-Weng Sin	[6] [10] [14] [15] [18] [19] [24]
18	Chi-sam Sou	[11]
19	He Gong Wei	[24]
20	Man-Chung Wong	[8]