Sai-Weng Sin

2008
7	EE	He Gong Wei, U. Fat Chio, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins: A power scalable 6-bit 1.2GS/s flash ADC with power on/off Track-and-Hold and preamplifier. ISCAS 2008: 5-8
2006
6	EE	Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins: A novel low-voltage finite-gain compensation technique for high-speed reset- and switched-opamp circuits. ISCAS 2006
5	EE	Jun-Xia Ma, Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins: A power-efficient 1.056 GS/s resolution-switchable 5-bit/6-bit flash ADC for UWB applications. ISCAS 2006
2005
4	EE	Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins: A novel very low-voltage SC-CMFB technique for fully-differential reset-opamp circuits. ISCAS (2) 2005: 1581-1584
3	EE	Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins: A novel low-voltage cross-coupled passive sampling branch for reset- and switched-opamp circuits. ISCAS (2) 2005: 1585-1588
2004
2		Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins: A generalized timing-skew-free, multi-phase clock generation platform for parallel sampled-data systems. ISCAS (1) 2004: 369-372
2003
1	EE	Sai-Weng Sin, Seng-Pan U., Rui Paulo Martins, José E. Franca: Timing-mismatch analysis in high-speed analog front-end with nonuniformly holding output. ISCAS (1) 2003: 129-132

Coauthor Index

1	U. Fat Chio	[7]
2	José E. Franca	[1]
3	Jun-Xia Ma	[5]
4	Rui Paulo Martins	[1] [2] [3] [4] [5] [6] [7]
5	Seng-Pan U.	[1] [2] [3] [4] [5] [6] [7]
6	He Gong Wei	[7]