| |
| 2009 | ||
|---|---|---|
| 1 | EE | R. Venkatraman, R. Castagnetti, Andres Teene, Benjamin Mbouombouo, S. Ramesh: Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design. ISQED 2009: 27-32 |
| 1 | R. Castagnetti | [1] |
| 2 | S. Ramesh (Sethu Ramesh) | [1] |
| 3 | Andres Teene | [1] |
| 4 | R. Venkatraman | [1] |