| 2005 |
|---|
| 9 | EE | S. Suchitra,
S. Sukthankar,
T. Srikanthan,
C. T. Clarke:
Elimination of sign precomputation in flat CORDIC.
ISCAS (4) 2005: 3319-3322 |
| 2003 |
|---|
| 8 | EE | N. Sudha,
T. Srikanthan,
Babu Mailachalam:
A VLSI architecture for 3-D self-organizing map based color quantization and its FPGA implementation.
Journal of Systems Architecture 48(11-12): 337-352 (2003) |
| 2002 |
|---|
| 7 | EE | S. K. Lam,
T. Srikanthan,
N. Goyal,
N. Tyagi:
Incorporating area-time flexibility to a binary signed-digit adder.
APCCAS (1) 2002: 485-489 |
| 6 | EE | S. K. Lam,
T. Srikanthan:
A linear approximation based hybrid approach for binary logarithmic conversion.
Microprocessors and Microsystems 26(8): 353-361 (2002) |
| 5 | EE | Babu Mailachalam,
T. Srikanthan:
Area-time issues in the VLSI implementation of self organizing map neural networks.
Microprocessors and Microsystems 26(9-10): 399-406 (2002) |
| 2000 |
|---|
| 4 | EE | Babu Mailachalam,
T. Srikanthan:
A Robust Parallel Architecture for Adaptive Color Quantization.
ITCC 2000: 164-173 |
| 1999 |
|---|
| 3 | EE | M. Bhardwaj,
T. Srikanthan,
C. T. Clarke:
A Reverse Converter for the 4-moduli Superset {2^n-1, 2^n, 2^n+1, 2^(n+1)+1}.
IEEE Symposium on Computer Arithmetic 1999: 168-175 |
| 2 | EE | M. Bhardwaj,
T. Srikanthan,
C. T. Clarke:
VLSI Costs of Arithmetic Parallelism: A Residue Reverse Conversion Perspectiv.
IEEE Symposium on Computer Arithmetic 1999: 176- |
| 1 | | Jimson Mathew,
D. Radhakrishnan,
T. Srikanthan:
Residue-to-binary arithmetic converter for moduli set {2n -1, 2n, 2n+1, 2n+1 -1}.
NSIP 1999: 185-188 |
