| 2004 |
|---|
| 8 | EE | Atsushi Nunome,
Hiroaki Hirata,
Haruo Niimi,
Kiyoshi Shibayama:
Performance evaluation of dynamic load balancing scheme with load prediction mechanism using the load growing acceleration for massively parallel computers.
Systems and Computers in Japan 35(11): 69-79 (2004) |
| 2002 |
|---|
| 7 | EE | Shuji Yamamura,
Tadafumi Kadota,
Hiroaki Hirata,
Haruo Niimi,
Kiyoshi Shibayama:
Evaluation of a data preload mechanism for a linked list structure.
Systems and Computers in Japan 33(3): 21-30 (2002) |
| 1987 |
|---|
| 6 | | Kiyoshi Shibayama,
Masaaki Yamamoto,
Hiroaki Hirata,
Yasushi Konoh,
Takanori Sanetoh,
Hiroshi Hagiwara:
KPR: A Logic Programming Language-Oriented Parallel Machine.
LP 1987: 113-131 |
| 1986 |
|---|
| 5 | | Shinji Tomita,
Kiyoshi Shibayama,
Toshiyuki Nakata,
Shinji Yuasa,
Hiroshi Hagiwara:
A Computer with Low-Level Parallelism QA-2: Its Applications to 3-D Graphics and Prolog/Lisp Machines.
ISCA 1986: 280-289 |
| 1983 |
|---|
| 4 | | Shinji Tomita,
Kiyoshi Shibayama,
Toshiaki Kitamura,
Toshiyuki Nakata,
Hiroshi Hagiwara:
A User-Microprogrammable, Local Host Computer With Low-Level Parallelism
ISCA 1983: 151-157 |
| 1980 |
|---|
| 3 | | Kiyoshi Shibayama,
Shinji Tomita,
Hiroshi Hagiwara,
Katsuhiro Yamazaki,
Toshiaki Kitamura:
Performance Evaluation and Improvement of a Dynamically Microprogrammable Computer with Low-Level Parallelism.
IFIP Congress 1980: 181-186 |
| 2 | | Hiroshi Hagiwara,
Shinji Tomita,
Shigeru Oyanagi,
Kiyoshi Shibayama:
A Dynamically Microprogammable Computer with Low-Level Parallelism.
IEEE Trans. Computers 29(7): 577-595 (1980) |
| 1977 |
|---|
| 1 | | Shinji Tomita,
Kiyoshi Shibayama,
Shigeru Oyanagi,
Hiroshi Hagiwara:
Hardware Organization of a Low Level Parallel Processor.
IFIP Congress 1977: 855-860 |
