| 2008 |
|---|
| 12 | EE | Shingo Yoshizawa,
Kazuto Nishi,
Yoshikazu Miyanaga:
Reconfigurable two-dimensional pipeline FFT processor in OFDM cognitive radio systems.
ISCAS 2008: 1248-1251 |
| 11 | EE | Shingo Yoshizawa,
Yasushi Yamauchi,
Yoshikazu Miyanaga:
A complete pipelined MMSE detection architecture in a 4x4 MIMO-OFDM receiver.
ISCAS 2008: 2486-2489 |
| 10 | EE | Shingo Yoshizawa,
Yasushi Yamauchi,
Yoshikazu Miyanaga:
VLSI Implementation of a Complete Pipeline MMSE Detector for a 4 x 4 MIMO-OFDM Receiver.
IEICE Transactions 91-A(7): 1757-1762 (2008) |
| 2007 |
|---|
| 9 | EE | Takayuki Sugawara,
Shingo Yoshizawa,
Yoshikazu Miyanaga:
Dynamic Reconfigurable Architecture for a Low-Power Despreader in VSF-OFCDM Systems.
ISCAS 2007: 2287-2290 |
| 8 | EE | Shingo Yoshizawa,
Yoshikazu Miyanaga:
Use of a Variable Wordlength Technique in an OFDM Receiver to Reduce Energy Dissipation.
ISCAS 2007: 3175-3178 |
| 2006 |
|---|
| 7 | EE | Shingo Yoshizawa,
Yoshikazu Miyanaga:
VLSI Implementation of a 600-Mbps MIMO-OFDM Wireless Communication System.
APCCAS 2006: 93-96 |
| 6 | EE | Shingo Yoshizawa,
Yoshikazu Miyanaga,
H. Ochi,
Y. Itoh,
N. Hataoka,
B. Sai,
N. Takayama,
M. Hirata:
300-Mbps OFDM baseband transceiver for wireless LAN systems.
ISCAS 2006 |
| 5 | EE | Naoya Wada,
Noboru Hayasaka,
Shingo Yoshizawa,
Yoshikazu Miyanaga:
Direct control on modulation spectrum for noise-robust speech recognition and spectral subtraction.
ISCAS 2006 |
| 4 | EE | Shingo Yoshizawa,
Yoshikazu Miyanaga:
Tunable word length architecture for low power wireless OFDM demodulator.
ISCAS 2006 |
| 3 | EE | Shingo Yoshizawa,
Yoshikazu Miyanaga:
Tunable Wordlength Architecture for a Low Power Wireless OFDM Demodulator.
IEICE Transactions 89-A(10): 2866-2873 (2006) |
| 2005 |
|---|
| 2 | EE | Yasuyuki Hatakawa,
Shingo Yoshizawa,
Yoshikazu Miyanaga:
Robust VLSI architecture for system-on-chip design and its implementation in Viterbi decoder.
ISCAS (1) 2005: 25-28 |
| 2004 |
|---|
| 1 | EE | Shingo Yoshizawa,
Naoya Wada,
Noboru Hayasaka,
Yoshikazu Miyanaga:
Scalable architecture for word HMM-based speech recognition.
ISCAS (3) 2004: 417-420 |
