Gordon R. Chiu

List of publications from the DBLP Bibliography Server - FAQ

2007

3 EE Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown: Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. IEEE Trans. VLSI Syst. 15(8): 895-903 (2007)

2006

2 EE Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown: Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs. ICCAD 2006: 135-142

1 EE Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown: Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. SLIP 2006: 3-8

2007
3	EE	Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown: Predicting Interconnect Delay for Physical Synthesis in a FPGA CAD Flow. IEEE Trans. VLSI Syst. 15(8): 895-903 (2007)
2006
2	EE	Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown: Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs. ICCAD 2006: 135-142
1	EE	Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown: Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. SLIP 2006: 3-8

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