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Seongjae Cho

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2008
5EESeongjae Cho, Il Han Park, Jung Hoon Lee, Jang-Gn Yun, Doo-Hyun Kim, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park: Establishing Read Operation Bias Schemes for 3-D Pillar Structure Flash Memory Devices to Overcome Paired Cell Interference (PCI). IEICE Transactions 91-C(5): 731-735 (2008)
4EEJang-Gn Yun, Il Han Park, Seongjae Cho, Jung Hoon Lee, Doo-Hyun Kim, Gil Sung Lee, Yoon Kim, Jong Duk Lee, Byung-Gook Park: Characterization of 2-bit Recessed Channel Memory with Lifted-Charge Trapping Node (L-CTN) Scheme. IEICE Transactions 91-C(5): 742-746 (2008)
2007
3EEHochul Lee, Youngchang Yoon, Seongjae Cho, Hyungcheol Shin: Accurate Extraction of the Trap Depth from RTS Noise Data by Including Poly Depletion Effect and Surface Potential Variation in MOSFETs. IEICE Transactions 90-C(5): 968-972 (2007)
2EEJong Pil Kim, Woo Young Choi, Jae Young Song, Seongjae Cho, Sang Wan Kim, Jong Duk Lee, Byung-Gook Park: Design and Simulation of Asymmetric MOSFETs. IEICE Transactions 90-C(5): 978-982 (2007)
1EESeongjae Cho, Jang-Gn Yun, Il Han Park, Jung Hoon Lee, Jong Pil Kim, Jong Duk Lee, Hyungcheol Shin, Byung-Gook Park: Analyses on Current Characteristics of 3-D MOSFET Determined by Junction Doping Profiles for Nonvolatile Memory Devices. IEICE Transactions 90-C(5): 988-993 (2007)

Coauthor Index

1Woo Young Choi [2]
2Doo-Hyun Kim [4] [5]
3Jong Pil Kim [1] [2]
4Sang Wan Kim [2]
5Yoon Kim [4]
6Gil Sung Lee [4]
7Hochul Lee [3]
8Jong Duk Lee [1] [2] [4] [5]
9Jung Hoon Lee [1] [4] [5]
10Byung-Gook Park [1] [2] [4] [5]
11Il Han Park [1] [4] [5]
12Hyungcheol Shin [1] [3] [5]
13Jae Young Song [2]
14Youngchang Yoon [3]
15Jang-Gn Yun [1] [4] [5]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)