| 2001 |
|---|
| 5 | EE | T. Enomoto,
A. Kotabe:
A fast motion estimation algorithm and low-power 0.13-um CMOS motion estimation circuits.
ISCAS (2) 2001: 449-452 |
| 1999 |
|---|
| 4 | EE | T. Enomoto,
Y. Sasajima,
A. Hirobe,
T. Ohsawa:
Fast motion estimation algorithm and low-power CMOS motion estimation array LSI for MPEG-2 encoding.
ISCAS (4) 1999: 203-206 |
| 1988 |
|---|
| 3 | | T. Shimizu,
T. Yoshida,
Y. Saito,
M. Matsuo,
T. Enomoto:
A 32-bit Microprocessor Based on the TRON Architecture: Design of the GMICRO/100.
COMPCON 1988: 30-35 |
| 1984 |
|---|
| 2 | EE | Takeshi Tokuda,
Jiro Korematsu,
Osamu Tomisawa,
S. Asai,
I. Ohkura,
T. Enomoto:
A Hierarchical Standard Cell Approach for Custom VLSI Design.
IEEE Trans. on CAD of Integrated Circuits and Systems 3(3): 172-177 (1984) |
| 1983 |
|---|
| 1 | EE | Takeshi Tokuda,
Kaoru Okazaki,
K. Sakashita,
I. Ohkura,
T. Enomoto:
Delay-Time Modeling for ED MOS Logic LSI.
IEEE Trans. on CAD of Integrated Circuits and Systems 2(3): 129-134 (1983) |
