| |
| 1983 | ||
|---|---|---|
| 2 | EE | Takeshi Tokuda, Kaoru Okazaki, K. Sakashita, I. Ohkura, T. Enomoto: Delay-Time Modeling for ED MOS Logic LSI. IEEE Trans. on CAD of Integrated Circuits and Systems 2(3): 129-134 (1983) |
| 1981 | ||
| 1 | Kaoru Okazaki, Toshihiko Yahara: Efficient Logic Verification and Test Validation for MOS LSI Circuits. ITC 1981: 530-535 | |
| 1 | T. Enomoto | [2] |
| 2 | I. Ohkura | [2] |
| 3 | K. Sakashita | [2] |
| 4 | Takeshi Tokuda | [2] |
| 5 | Toshihiko Yahara | [1] |