M. Redekopp
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2000
1
EE
M. Redekopp,
Andreas Dandalis
: A Parallel Pipelined SAT Solver for FPGAs.
FPL 2000
: 462-468
Coauthor
Index
1
Andreas Dandalis
[
1
]
Copyright ©
Sun May 17 03:24:02 2009 by
Michael Ley
(
ley@uni-trier.de
)
