| |
| 2007 | ||
|---|---|---|
| 3 | EE | Nivedita Deshmukh, Sameer Wadhwa: A Meta Model for Iterative Development of Requirements Leveraging. RE 2007: 343-349 |
| 2000 | ||
| 2 | EE | Reetinder P. S. Sidhu, Sameer Wadhwa, Alessandro Mei, Viktor K. Prasanna: A Self-Reconfigurable Gate Array Architecture. FPL 2000: 106-120 |
| 1 | EE | Sameer Wadhwa, Andreas Dandalis: Efficient Self-Reconfigurable Implementations Using On-chip Memory. FPL 2000: 443-448 |
| 1 | Andreas Dandalis | [1] |
| 2 | Nivedita Deshmukh | [3] |
| 3 | Alessandro Mei | [2] |
| 4 | Viktor K. Prasanna (V. K. Prasanna Kumar) | [2] |
| 5 | Reetinder P. S. Sidhu | [2] |