2006 | ||
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2 | EE | H. C. Yeo, N. Guo, H. Du, W. M. Huang, X. M. Jian: Characterisation of IC packaging interfaces and loading effects. Microelectronics Reliability 46(9-11): 1892-1897 (2006) |
2001 | ||
1 | EE | D. Zhou, Wei Li, W. Cai, N. Guo: An efficient balanced truncation realization algorithm for interconnect model order reduction. ISCAS (5) 2001: 383-386 |
1 | W. Cai | [1] |
2 | H. Du | [2] |
3 | W. M. Huang | [2] |
4 | X. M. Jian | [2] |
5 | Wei Li | [1] |
6 | H. C. Yeo | [2] |
7 | D. Zhou | [1] |