| 2008 |
|---|
| 9 | EE | Shen-Fu Hsiao,
Ming-Yu Tsai,
Chia-Sheng Wen:
Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction.
ISCAS 2008: 2022-2025 |
| 2006 |
|---|
| 8 | EE | Shen-Fu Hsiao,
Sze-Yun Lin,
Tze-Chong Cheng,
Ming-Yu Tsai:
An Automatic Cache Generator Based on Content-Addressable Memory.
APCCAS 2006: 1313-1316 |
| 7 | EE | Shen-Fu Hsiao,
Ming-Yu Tsai,
Chia-Sheng Wen:
Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits.
APCCAS 2006: 1631-1634 |
| 6 | EE | Shen-Fu Hsiao,
Yo-Chi Chen,
Ming-Yu Tsai,
Tze-Chong Cheng:
Novel Memory Organization and Circuit Designs for Efficient Data Access in Applications of 3D Graphics and Multimedia Coding.
MTDT 2006: 34-42 |
| 2005 |
|---|
| 5 | EE | Ming-Yu Tsai,
Li-Chen Fu,
Ta-Chiun Chou:
Automatic Negotiation with Mediated Agents in E-commerce Marketplace.
EEE 2005: 50-53 |
| 4 | EE | Shen-Fu Hsiao,
Ming-Yu Tsai,
Ming-Chih Chen,
Chia-Sheng Wen:
An efficient pass-transistor-logic synthesizer using multiplexers and inverters only.
ISCAS (3) 2005: 2433-2436 |
| 3 | EE | Tso-Bing Juang,
Shen-Fu Hsiao,
Ming-Yu Tsai,
Jenq-Shiun Jan:
A Cell-Driven Multiplier Generator with Delay Optimization of Partial Products Compression and an Efficient Partition Technique for the Final Addition.
IEICE Transactions 88-D(7): 1464-1471 (2005) |
| 2004 |
|---|
| 2 | | Shun-Fa Chang,
Li-Chen Fu,
Ming-Yu Tsai:
Automatic Integration of Inter-Enterprise Processes with Hierarchical Broker Framework.
ICEIS (4) 2004: 62-69 |
| 2002 |
|---|
| 1 | EE | Tso-Bing Juang,
Jeng-Hsiun Jan,
Ming-Yu Tsai,
Shen-Fu Hsiao:
Partition methodology for the final adder in a tree-structure parallel multiplier generator.
APCCAS (1) 2002: 471-474 |
