| |
| 2008 | ||
|---|---|---|
| 3 | EE | Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen: Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction. ISCAS 2008: 2022-2025 |
| 2006 | ||
| 2 | EE | Shen-Fu Hsiao, Ming-Yu Tsai, Chia-Sheng Wen: Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits. APCCAS 2006: 1631-1634 |
| 2005 | ||
| 1 | EE | Shen-Fu Hsiao, Ming-Yu Tsai, Ming-Chih Chen, Chia-Sheng Wen: An efficient pass-transistor-logic synthesizer using multiplexers and inverters only. ISCAS (3) 2005: 2433-2436 |
| 1 | Ming-Chih Chen | [1] |
| 2 | Shen-Fu Hsiao | [1] [2] [3] |
| 3 | Ming-Yu Tsai | [1] [2] [3] |