| 2008 |
|---|
| 13 | | Masaya Yoshikawa,
Hidekazu Terai:
Hardware Architecture of Pheromone-Balance Aware Ant Colony Optimization.
GEM 2008: 135-139 |
| 12 | EE | Masaya Yoshikawa,
Hidekazu Terai:
Route selection algorithm based on integer operation Ant Colony Optimization.
IRI 2008: 17-21 |
| 11 | EE | Akihiro Nakamura,
Masahide Kawarasaki,
Kouta Ishibashi,
Masaya Yoshikawa,
Takeshi Fujino:
Regular Fabric of Via Programmable Logic Device Using EXclusive-or Array (VPEX) for EB Direct Writing.
IEICE Transactions 91-C(4): 509-516 (2008) |
| 2007 |
|---|
| 10 | EE | Masaya Yoshikawa,
Hidekazu Terai:
Architecture for high-speed Ant Colony Optimization.
IRI 2007: 1-5 |
| 9 | EE | Masaya Yoshikawa,
Hidekazu Terai:
Hierarchical Parallel Placement Using a Genetic Algorithm for Realizing Low Power Consumption.
JACIII 11(2): 168-175 (2007) |
| 2006 |
|---|
| 8 | | Masaya Yoshikawa,
Hidekazu Terai:
Co-evolutionary robotics using two kinds of neural networks.
CAINE 2006: 330-334 |
| 7 | | Masaya Yoshikawa,
Masahiro Fukui,
Hidekazu Terai:
Immune Algorithm Processor.
Computers and Their Applications 2006: 13-18 |
| 6 | EE | Masaya Yoshikawa,
Hidekazu Terai:
Apriori, Association Rules, Data Mining, Frequent Itemsets Mining (FIM), Parallel Computing.
SERA 2006: 95-100 |
| 5 | EE | Masaya Yoshikawa,
Hidekazu Terai:
Dedicated Floorplanning Engine Architecture Based on Genetic Algorithm and Evaluation.
JACIII 10(1): 112-120 (2006) |
| 2005 |
|---|
| 4 | EE | Masaya Yoshikawa,
Hidekazu Terai:
Performance driven placement technique based on collaboration of software and hardware.
Congress on Evolutionary Computation 2005: 1570-1575 |
| 3 | EE | Masaya Yoshikawa,
Hidekazu Terai:
A Hierarchical Parallel Placement Technique based on Genetic Algorithm.
ISDA 2005: 302-307 |
| 2 | EE | Masaya Yoshikawa,
Hidekazu Terai:
Asynchronous Parallel Genetic Algorithm for Congestion-Driven Placement Technique.
SERA 2005: 130-136 |
| 2004 |
|---|
| 1 | | Tetsuya Imai,
Masaya Yoshikawa,
Hidekazu Terai,
Hironori Yamauchi:
VLSI processor architecture for real-time GA processing and PE-VLSI design.
ISCAS (3) 2004: 625-628 |
