| 2001 |
|---|
| 6 | EE | R.-Ming Shiu,
Hui-Yue Hwang,
Jean Jyh-Jiun Shann:
Aggressive Schduling for Memory Accesses of CISC Superscalar Microprocessors.
J. Inf. Sci. Eng. 17(5): 787-803 (2001) |
| 2000 |
|---|
| 5 | EE | R.-Ming Shiu,
Neng-Pin Lu,
Chung-Ping Chung:
Applying stack simulation for branch target buffers.
Journal of Systems and Software 52(1): 67-78 (2000) |
| 1998 |
|---|
| 4 | EE | S.-K. Cheng,
R.-Ming Shiu,
Jean Jyh-Jiun Shann:
Decoding Unit with High Issue Rate for X86 Superscalar Microprocessors.
ICPADS 1998: 488-495 |
| 3 | EE | Hui-Yue Hwang,
R.-Ming Shiu,
Jean Jyh-Jiun Shann:
An X86 Load/Store Unit with Aggressive Scheduling of Load/Store Operations.
ICPADS 1998: 496-503 |
| 1997 |
|---|
| 2 | EE | Shyh-An Chi,
R.-Ming Shiu,
Jih-Ching Chiu,
Si-En Chang,
Chung-Ping Chung:
Instruction Cache Prefetching with Extended BTB.
ICPADS 1997: 360- |
| 1996 |
|---|
| 1 | EE | Chang-Chung Liu,
R.-Ming Shiu,
Chung-Ping Chung:
Register renaming for x86 superscalar design.
ICPADS 1996: 336-343 |
