| 2007 |
|---|
| 11 | EE | Hans Kristian Otnes Berge,
Philipp Häfliger:
High-Speed Serial AER on FPGA.
ISCAS 2007: 857-860 |
| 10 | EE | Philipp Häfliger:
Adaptive WTA With an Analog VLSI Neuromorphic Learning Chip.
IEEE Transactions on Neural Networks 18(2): 551-572 (2007) |
| 2005 |
|---|
| 9 | EE | Mehdi Azadmehr,
Jens Petter Abrahamsen,
Philipp Häfliger:
A foveated AER imager chip [address event representation].
ISCAS (3) 2005: 2751-2754 |
| 8 | EE | Håvard Kolle Riis,
Philipp Häfliger:
An Asynchronous 4-to-4 AER Mapper.
IWANN 2005: 494-501 |
| 7 | EE | Rafael Serrano-Gotarredona,
Matthias Oster,
Patrick Lichtsteiner,
Alejandro Linares-Barranco,
Rafael Paz-Vicente,
Francisco Gomez-Rodriguez,
Håvard Kolle Riis,
Tobi Delbrück,
Shih-Chii Liu,
S. Zahnd,
Adrian M. Whatley,
Rodney J. Douglas,
Philipp Häfliger,
Gabriel Jiménez-Moreno,
Antón Civit,
Teresa Serrano-Gotarredona,
Antonio Acosta-Jimenez,
Bernabé Linares-Barranco:
AER Building Blocks for Multi-Layer Multi-Chip Neuromorphic Vision Systems.
NIPS 2005 |
| 2004 |
|---|
| 6 | | Jens Petter Abrahamsen,
Philipp Häfliger,
Tor Sverre Lande:
A time domain winner-take-all network of integrate-and-fire neurons.
ISCAS (5) 2004: 361-364 |
| 5 | | Håvard Kolle Riis,
Philipp Häfliger:
Spike based learning with weak multi-level static memory.
ISCAS (5) 2004: 393-396 |
| 2003 |
|---|
| 4 | EE | Philipp Häfliger,
Håvard Kolle Riis:
A multi-level static memory cell.
ISCAS (1) 2003: 25-28 |
| 1999 |
|---|
| 3 | EE | Philipp Häfliger:
Learning a temporal code.
ESANN 1999: 423-428 |
| 2 | EE | Philipp Häfliger,
C. Rasche:
Floating gate analog memory for parameter and variable storage in a learning silicon neuron.
ISCAS (2) 1999: 416-419 |
| 1996 |
|---|
| 1 | EE | Philipp Häfliger,
Misha Mahowald,
Lloyd Watts:
A Spike Based Learning Neuron in Analog VLSI.
NIPS 1996: 692-698 |
