2004 | ||
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1 | EE | C. F. Tsang, C. Y. Li, A. Krishnamoorthy, Y. J. Su, H. Y. Li, L. Y. Wong, W. H. Li, L. J. Tang, K. Y. Ee: Impact of barrier deposition process on electrical and reliability performance of Cu/CVD low k SiOCH metallization. Microelectronics Journal 35(9): 693-700 (2004) |
1 | K. Y. Ee | [1] |
2 | A. Krishnamoorthy | [1] |
3 | H. Y. Li | [1] |
4 | W. H. Li | [1] |
5 | Y. J. Su | [1] |
6 | L. J. Tang | [1] |
7 | C. F. Tsang | [1] |
8 | L. Y. Wong | [1] |