S. Raja
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2008
1
EE
S. Raja,
F. Varadi
,
Murat R. Becer
,
Joao Geada
: Transistor level gate modeling for accurate and fast timing, noise, and power analysis.
DAC 2008
: 456-461
Coauthor
Index
1
Murat R. Becer
[
1
]
2
Joao Geada
[
1
]
3
F. Varadi
[
1
]
Copyright ©
Sun May 17 03:24:02 2009 by
Michael Ley
(
ley@uni-trier.de
)
