| 2009 |
|---|
| 6 | EE | Mahta Haghi,
Jeff Draper:
The effect of design parameters on single-event upset sensitivity of MOS current mode logic.
ACM Great Lakes Symposium on VLSI 2009: 233-238 |
| 2007 |
|---|
| 5 | EE | Riaz Naseer,
Jeff Draper,
Younes Boulghassoul,
Sandeepan DasGupta,
Art Witulski:
Critical charge and set pulse widths for combinational logic in commercial 90nm cmos technology.
ACM Great Lakes Symposium on VLSI 2007: 227-230 |
| 4 | EE | Riaz Naseer,
Younes Boulghassoul,
Jeff Draper,
Sandeepan DasGupta,
Art Witulski:
Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAM.
ISCAS 2007: 1879-1882 |
| 2006 |
|---|
| 3 | EE | Rashed Zafar Bhatti,
Monty Denneau,
Jeff Draper:
2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology.
ACM Great Lakes Symposium on VLSI 2006: 198-203 |
| 2 | EE | Riaz Naseer,
Jeff Draper:
DF-DICE: a scalable solution for soft error tolerant circuit design.
ISCAS 2006 |
| 1 | EE | Rashed Zafar Bhatti,
Monty Denneau,
Jeff Draper:
Phase measurement and adjustment of digital signals using random sampling technique.
ISCAS 2006 |
