| 2007 |
|---|
| 7 | EE | Håkan Zeffer,
Erik Hagersten:
A case for low-complexity MP architectures.
SC 2007: 19 |
| 2006 |
|---|
| 6 | EE | Håkan Zeffer,
Zoran Radovic,
Martin Karlsson,
Erik Hagersten:
TMA: a trap-based memory architecture.
ICS 2006: 259-268 |
| 5 | EE | Pavlos Petoumenos,
Georgios Keramidas,
Håkan Zeffer,
Stefanos Kaxiras,
Erik Hagersten:
Modeling Cache Sharing on Chip Multiprocessor Architectures.
IISWC 2006: 160-171 |
| 4 | EE | Håkan Zeffer,
Zoran Radovic,
Erik Hagersten:
Exploiting locality: a flexible DSM approach.
IPDPS 2006 |
| 3 | EE | Erik Berg,
Håkan Zeffer,
Erik Hagersten:
A statistical multiprocessor cache model.
ISPASS 2006: 89-99 |
| 2005 |
|---|
| 2 | | Dan Wallin,
Håkan Zeffer,
Martin Karlsson,
Erik Hagersten:
VASA: A Simulator Infrastructure with Adjustable Fidelity.
IASTED PDCS 2005: 554-563 |
| 2004 |
|---|
| 1 | EE | Håkan Zeffer,
Zoran Radovic,
Oskar Grenholm,
Erik Hagersten:
Exploiting Spatial Store Locality Through Permission Caching in Software DSMs.
Euro-Par 2004: 551-560 |
