1998 | ||
---|---|---|
1 | EE | David Jefferson, Srinivas Reddy, Christopher Lane, Ninh Ngo, Wanli Chang, Manuel Mijia, Ketan Zaveri, Cameron McClintock, Richard Cliff: A 100 MHz PLL Implemented on a 100K Gate Programmable Logic Device (Abstract). FPGA 1998: 256 |
1 | Wanli Chang | [1] |
2 | Richard Cliff | [1] |
3 | David Jefferson | [1] |
4 | Christopher Lane | [1] |
5 | Cameron McClintock | [1] |
6 | Manuel Mijia | [1] |
7 | Ninh Ngo | [1] |
8 | Srinivas Reddy | [1] |