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| 1998 | ||
|---|---|---|
| 2 | EE | David Jefferson, Srinivas Reddy, Christopher Lane, Ninh Ngo, Wanli Chang, Manuel Mijia, Ketan Zaveri, Cameron McClintock, Richard Cliff: A 100 MHz PLL Implemented on a 100K Gate Programmable Logic Device (Abstract). FPGA 1998: 256 |
| 1995 | ||
| 1 | J. Turner, Richard Cliff, W. Leong, Cameron McClintock, Ninh Ngo, K. Nguyen, C. K. Sung, B. Wang, J. Watson: Migration of a Dual Granularity Globally Interconnected PLD Architecture to a 0.5 µm TLM Process. FPL 1995: 15-20 | |
| 1 | Wanli Chang | [2] |
| 2 | Richard Cliff | [1] [2] |
| 3 | David Jefferson | [2] |
| 4 | Christopher Lane | [2] |
| 5 | W. Leong | [1] |
| 6 | Cameron McClintock | [1] [2] |
| 7 | Manuel Mijia | [2] |
| 8 | K. Nguyen | [1] |
| 9 | Srinivas Reddy | [2] |
| 10 | C. K. Sung | [1] |
| 11 | J. Turner | [1] |
| 12 | B. Wang | [1] |
| 13 | J. Watson | [1] |
| 14 | Ketan Zaveri | [2] |