| 2006 |
|---|
| 6 | EE | Yuichi Nakamura,
Mitsuru Tagata,
Takumi Okamoto,
Shigeyoshi Tawada,
Ko Yoshikawa:
Budgeting-free hierarchical design method for large scale and high-performance LSIs.
DAC 2006: 955-958 |
| 5 | EE | Ko Yoshikawa,
Shigeto Inui,
Yasuhiko Hagihara,
Yuichi Nakamura,
Takeshi Yoshimura:
Domino Logic Synthesis System and its Applications.
Journal of Circuits, Systems, and Computers 15(2): 277-287 (2006) |
| 2005 |
|---|
| 4 | EE | Yuichi Nakamura,
Ko Yoshikawa,
Takeshi Yoshimura:
An Engineering Change Orders Design Method Based on Patchwork-Like Partitioning for High Performance LSIs.
IEICE Transactions 88-A(12): 3351-3357 (2005) |
| 2004 |
|---|
| 3 | EE | Ko Yoshikawa,
Yasuhiko Hagihara,
Keisuke Kanamaru,
Yuichi Nakamura,
Shigeto Inui,
Takeshi Yoshimura:
Timing optimization by replacing flip-flops to latches.
ASP-DAC 2004: 186-191 |
| 2 | EE | Yuichi Nakamura,
Kohei Hosokawa,
Ichiro Kuroda,
Ko Yoshikawa,
Takeshi Yoshimura:
A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication.
DAC 2004: 299-304 |
| 1991 |
|---|
| 1 | EE | Ko Yoshikawa,
Hiroshi Ichiryu,
Hisato Tanishita,
Shigenobu Suzuki,
Nobuyoshi Nomizu,
Akira Kondoh:
Timing Optimization on Mapped Circuits.
DAC 1991: 112-117 |
