| 2006 |
|---|
| 7 | EE | Teruo Tanaka,
Takahiro Katagiri,
Toshitsugu Yuba:
d-Spline Based Incremental Parameter Estimation in Automatic Performance Tuning.
PARA 2006: 986-995 |
| 1998 |
|---|
| 6 | | Frederico B. Maciel,
Nobutoshi Sagawa,
Teruo Tanaka:
Dynamic Gateways: A Novel Approach to Improve Networking Performance and Availability on Parallel Servers.
HPCN Europe 1998: 678-687 |
| 1997 |
|---|
| 5 | EE | Yoshiko Yasuda,
Hiroaki Fujii,
Hideya Akashi,
Yasuhiro Inagami,
Teruo Tanaka,
Junji Nakagoshi,
Hideo Wada,
Tsutomu Sumimoto:
Deadlock-Free Fault-tolerant Routing in the Multi-dimensional Crossbar Network and Its Implementation for the Hitachi SR2201.
IPPS 1997: 346-352 |
| 1994 |
|---|
| 4 | EE | Katsuyoshi Kitai,
Tadaaki Isobe,
Tadayuki Sakakibara,
Shigeko Yazawa,
Yoshiko Tamaki,
Teruo Tanaka,
Kouichi Ishii:
Distributed storage control unit for the Hitachi S-3800 multivector supercomputer.
International Conference on Supercomputing 1994: 1-10 |
| 1993 |
|---|
| 3 | EE | Tadayuki Sakakibara,
Katsuyoshi Kitai,
Tadaaki Isobe,
Shigeko Yazawa,
Teruo Tanaka,
Yasuhiro Inagami,
Yoshiko Tamaki:
Scalable Parallel Memory Architecture with a Skew Scheme.
International Conference on Supercomputing 1993: 157-166 |
| 2 | EE | Katsuyoshi Kitai,
Tadaaki Isobe,
Yoshikazu Tanaka,
Yoshiko Tamaki,
Masakazu Fukagawa,
Teruo Tanaka,
Yasuhiro Inagami:
Parallel Processing Architecture for the Hitachi S-3800 Shared-Memory Vector Multiprocessor.
International Conference on Supercomputing 1993: 288-297 |
| 1992 |
|---|
| 1 | | Naoki Hamanaka,
Junji Nakagoshi,
Teruo Tanaka:
Reducing Network Hardware Quantity by Employing Multi-Processor Cluster Structure in Distributed Memory Parallel Processors.
CONPAR 1992: 25-30 |
