| 2007 |
|---|
| 10 | EE | Yasuhiro Sugimoto,
Koichi Osuka:
Hierarchical implicit feedback structure in passive dynamic walking.
IROS 2007: 2217-2222 |
| 9 | EE | Hiroki Sakurai,
Shigeto Tanaka,
Yasuhiro Sugimoto:
A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture.
IEICE Transactions 90-A(10): 2272-2279 (2007) |
| 8 | EE | Hiroki Sakurai,
Yasuhiro Sugimoto:
The Realization of an Area-Efficient CMOS Bandgap Reference Circuit with Less than 1.25 V of Output Voltage Using a Fractional VBE Amplification Scheme.
IEICE Transactions 90-C(2): 499-506 (2007) |
| 7 | EE | Toru Choi,
Tatsuya Sakamoto,
Yasuhiro Sugimoto:
A Study to Realize a 1-V Operational Passive Sigma-Delta Modulator by Using a 90 nm CMOS Process.
IEICE Transactions 90-C(6): 1304-1306 (2007) |
| 2006 |
|---|
| 6 | EE | Yasuhiro Sugimoto,
Yuji Gohda,
Shigeto Tanaka:
A Study to Realize a CMOS Pipelined Current-Mode A-to-D Converter for Video Applications.
IEICE Transactions 89-C(6): 811-813 (2006) |
| 2005 |
|---|
| 5 | EE | Shigeto Tanaka,
Yuji Gohda,
Yasuhiro Sugimoto:
The realization of a mismatch-free and 1.5-bit over-sampling pipelined ADC.
ISCAS (6) 2005: 6194-6197 |
| 4 | EE | Hiroki Sakurai,
Yasuhiro Sugimoto:
Analysis and Design of a Current-Mode PWM Buck Converter Adopting the Output-Voltage Independent Second-Order Slope Compensation Scheme.
IEICE Transactions 88-A(2): 490-497 (2005) |
| 3 | EE | Shinya Kawada,
Yasuhiro Sugimoto:
A 500-MHz and 60-dB Omega CMOS Transimpedance Amplifier Using the New Feedforward Stabilization Technique.
IEICE Transactions 88-C(6): 1285-1287 (2005) |
| 2002 |
|---|
| 2 | EE | Koichi Osuka,
Yasuhiro Sugimoto:
Stabilization of quasi-passive-dynamic-walking based on delayed feedback control.
ICARCV 2002: 803-808 |
| 1995 |
|---|
| 1 | | Yasuhiro Sugimoto:
A 1.6V 10-Bit 20MHz Current-Mode Sample and Hold Circuit.
ISCAS 1995: 1332-1335 |
