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Shigeto Tanaka

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2007
3EEHiroki Sakurai, Shigeto Tanaka, Yasuhiro Sugimoto: A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture. IEICE Transactions 90-A(10): 2272-2279 (2007)
2006
2EEYasuhiro Sugimoto, Yuji Gohda, Shigeto Tanaka: A Study to Realize a CMOS Pipelined Current-Mode A-to-D Converter for Video Applications. IEICE Transactions 89-C(6): 811-813 (2006)
2005
1EEShigeto Tanaka, Yuji Gohda, Yasuhiro Sugimoto: The realization of a mismatch-free and 1.5-bit over-sampling pipelined ADC. ISCAS (6) 2005: 6194-6197

Coauthor Index

1Yuji Gohda [1] [2]
2Hiroki Sakurai [3]
3Yasuhiro Sugimoto [1] [2] [3]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)