| |
| 2007 | ||
|---|---|---|
| 3 | EE | Hiroki Sakurai, Shigeto Tanaka, Yasuhiro Sugimoto: A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture. IEICE Transactions 90-A(10): 2272-2279 (2007) |
| 2006 | ||
| 2 | EE | Yasuhiro Sugimoto, Yuji Gohda, Shigeto Tanaka: A Study to Realize a CMOS Pipelined Current-Mode A-to-D Converter for Video Applications. IEICE Transactions 89-C(6): 811-813 (2006) |
| 2005 | ||
| 1 | EE | Shigeto Tanaka, Yuji Gohda, Yasuhiro Sugimoto: The realization of a mismatch-free and 1.5-bit over-sampling pipelined ADC. ISCAS (6) 2005: 6194-6197 |
| 1 | Yuji Gohda | [1] [2] |
| 2 | Hiroki Sakurai | [3] |
| 3 | Yasuhiro Sugimoto | [1] [2] [3] |