| |
| 2007 | ||
|---|---|---|
| 3 | EE | Hiroki Sakurai, Shigeto Tanaka, Yasuhiro Sugimoto: A Digitally Assisted Gain and Offset Error Cancellation Technique for a CMOS Pipelined ADC with a 1.5-bit Bit-Block Architecture. IEICE Transactions 90-A(10): 2272-2279 (2007) |
| 2 | EE | Hiroki Sakurai, Yasuhiro Sugimoto: The Realization of an Area-Efficient CMOS Bandgap Reference Circuit with Less than 1.25 V of Output Voltage Using a Fractional VBE Amplification Scheme. IEICE Transactions 90-C(2): 499-506 (2007) |
| 2005 | ||
| 1 | EE | Hiroki Sakurai, Yasuhiro Sugimoto: Analysis and Design of a Current-Mode PWM Buck Converter Adopting the Output-Voltage Independent Second-Order Slope Compensation Scheme. IEICE Transactions 88-A(2): 490-497 (2005) |
| 1 | Yasuhiro Sugimoto | [1] [2] [3] |
| 2 | Shigeto Tanaka | [3] |