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2006 | ||
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1 | EE | Ales Smrcka, Vojtech Rehák, Tomás Vojnar, David Safránek, Petr Matousek, Z. Rehák: Verifying VHDL Designs with Multiple Clocks in SMV. FMICS/PDMC 2006: 148-164 |
1 | Petr Matousek | [1] |
2 | Vojtech Rehák | [1] |
3 | David Safránek | [1] |
4 | Ales Smrcka | [1] |
5 | Tomás Vojnar | [1] |