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Z. Rehák

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2006
1EEAles Smrcka, Vojtech Rehák, Tomás Vojnar, David Safránek, Petr Matousek, Z. Rehák: Verifying VHDL Designs with Multiple Clocks in SMV. FMICS/PDMC 2006: 148-164

Coauthor Index

1Petr Matousek [1]
2Vojtech Rehák [1]
3David Safránek [1]
4Ales Smrcka [1]
5Tomás Vojnar [1]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)