| 2009 |
|---|
| 8 | EE | Laura Bozzelli,
Mojmír Kretínský,
Vojtech Rehák,
Jan Strejcek:
On decidability of LTL model checking for process rewrite systems.
Acta Inf. 46(1): 1-28 (2009) |
| 2008 |
|---|
| 7 | EE | Mojmír Kretínský,
Vojtech Rehák,
Jan Strejcek:
Petri nets are less expressive than state-extended PA.
Theor. Comput. Sci. 394(1-2): 134-140 (2008) |
| 2006 |
|---|
| 6 | EE | Ales Smrcka,
Vojtech Rehák,
Tomás Vojnar,
David Safránek,
Petr Matousek,
Z. Rehák:
Verifying VHDL Designs with Multiple Clocks in SMV.
FMICS/PDMC 2006: 148-164 |
| 5 | EE | Laura Bozzelli,
Mojmír Kretínský,
Vojtech Rehák,
Jan Strejcek:
On Decidability of LTL Model Checking for Process Rewrite Systems.
FSTTCS 2006: 248-259 |
| 4 | EE | Mojmír Kretínský,
Vojtech Rehák,
Jan Strejcek:
Refining the Undecidability Border of Weak Bisimilarity.
Electr. Notes Theor. Comput. Sci. 149(1): 17-36 (2006) |
| 2005 |
|---|
| 3 | EE | Mojmír Kretínský,
Vojtech Rehák,
Jan Strejcek:
Reachability of Hennessy-Milner Properties for Weakly Extended PRS.
FSTTCS 2005: 213-224 |
| 2004 |
|---|
| 2 | EE | Mojmír Kretínský,
Vojtech Rehák,
Jan Strejcek:
Extended Process Rewrite Systems: Expressiveness and Reachability.
CONCUR 2004: 355-370 |
| 1 | EE | Mojmír Kretínský,
Vojtech Rehák,
Jan Strejcek:
On Extensions of Process Rewrite Systems: Rewrite Systems with Weak Finite-State Unit.
Electr. Notes Theor. Comput. Sci. 98: 75-88 (2004) |
