| |
| 2009 | ||
|---|---|---|
| 2 | EE | Hui Wang, Rama Sangireddy, Sandeep Baldawa: Optimizing Instruction Scheduling through Combined In-Order and O-O-O Execution in SMT Processors. IEEE Trans. Parallel Distrib. Syst. 20(3): 389-403 (2009) |
| 2008 | ||
| 1 | EE | Hui Wang, Sandeep Baldawa, Rama Sangireddy: Dynamic Error Detection for Dependable Cache Coherency in Multicore Architectures. VLSI Design 2008: 279-285 |
| 1 | Rama Sangireddy | [1] [2] |
| 2 | Hui Wang | [1] [2] |