2006 |
21 | EE | Tadaaki Tanimoto,
Seiji Yamaguchi,
Akio Nakata,
Teruo Higashino:
A real time budgeting method for module-level-pipelined bus based system using bus scenarios.
DAC 2006: 37-42 |
20 | EE | Akio Nakata,
Tadaaki Tanimoto,
Suguru Sasaki,
Teruo Higashino:
A Timed Failure Equivalence Preserving Abstraction for Parametric Time-interval Automata.
Int. J. Found. Comput. Sci. 17(4): 833-850 (2006) |
2005 |
19 | EE | Takaaki Umedu,
Shigeharu Urata,
Akio Nakata,
Teruo Higashino:
Automatic Decomposition of Java Program for Implementation on Mobile Terminals.
AINA 2005: 544-549 |
18 | EE | Tadaaki Tanimoto,
Akio Nakata,
Hideaki Hashimoto,
Teruo Higashino:
Double Depth First Search Based Parametric Analysis for Parametric Time-Interval Automata.
IEICE Transactions 88-A(11): 3007-3021 (2005) |
2004 |
17 | EE | Tadaaki Tanimoto,
Suguru Sasaki,
Akio Nakata,
Teruo Higashino:
A Global Timed Bisimulation Preserving Abstraction for Parametric Time-Interval Automata.
ATVA 2004: 179-195 |
16 | EE | Tomoya Kitani,
Yoshifumi Takamoto,
Keiichi Yasumoto,
Akio Nakata,
Teruo Higashino:
A Flexible and High-Reliable HW/SW Co-Design Method for Real-Time Embedded Systems.
RTSS 2004: 437-446 |
15 | EE | Takanori Mori,
Akio Nakata,
Teruo Higashino:
A Method for Designing Multimedia Protocols using Both Parametric Model Checking and Functional Testing.
Stud. Inform. Univ. 3(2): 231- (2004) |
2003 |
14 | EE | Tomoya Kitani,
Yoshifumi Takamoto,
Isao Naka,
Keiichi Yasumoto,
Akio Nakata,
Teruo Higashino:
Design and Implementation of Priority Queuing Mechanism on FPGA Using Concurrent Periodic EFSMs and Parametric Model Checking.
FPL 2003: 1145-1148 |
13 | EE | Takanori Mori,
Hirotaka Otsuka,
Nobuo Funabiki,
Akio Nakata,
Teruo Higashino:
A test sequence generation method for communication protocols using the SAT algorithm.
Systems and Computers in Japan 34(11): 20-29 (2003) |
2002 |
12 | EE | Takaaki Umedu,
Yoshiki Terashima,
Keiichi Yasumoto,
Akio Nakata,
Teruo Higashino,
Kenichi Taniguchi:
A Language for Describing Wireless Mobile Applications with Dynamic Establishment of Multi-way Synchronization Channels.
FME 2002: 607-624 |
11 | EE | Masayuki Kirimura,
Yoshifumi Takamoto,
Takanori Mori,
Keiichi Yasumoto,
Akio Nakata,
Teruo Higashino:
Design and Implementation of FPGA Circuits for High Speed Network Monitors.
FPL 2002: 393-403 |
10 | EE | Makoto Yamada,
Takanori Mori,
Atsushi Fukada,
Akio Nakata,
Teruo Higashino:
A Method for Functional Testing of Media Synchronization Protocols.
ICOIN (2) 2002: 539-550 |
9 | EE | Keiichi Yasumoto,
Takaaki Umedu,
Hirozumi Yamaguchi,
Akio Nakata,
Teruo Higashino:
Protocol animation based on event-driven visualization scenarios in real-time LOTOS.
Computer Networks 40(5): 639-663 (2002) |
2001 |
8 | | Akio Nakata,
Teruo Higashino:
Deriving Parameter Conditions for Periodic Timed Automata Satisfying Real-Time Temporal Logic Formulas.
FORTE 2001: 151-168 |
7 | EE | Atsushi Fukada,
Akio Nakata,
Junji Kitamichi,
Teruo Higashino,
Ana R. Cavalli:
A Conformance Testing Method for Communication Protocols Modeled as Concurrent DFSMs.
ICOIN 2001: 155-162 |
1999 |
6 | | Teruo Higashino,
Akio Nakata,
Kenichi Taniguchi,
Ana R. Cavalli:
Generating Test Cases for a Timed I/O Automaton Model.
IWTCS 1999: 197-214 |
1998 |
5 | EE | Akio Nakata,
Teruo Higashino,
Kenichi Taniguchi:
Protocol Synthesis from Context-Free Processes Using Event Structures.
RTCSA 1998: 173-180 |
1996 |
4 | | Akio Nakata,
Teruo Higashino,
Kenichi Taniguchi:
Time-Action Alternating Model for Timed LOTOS and its Symbolic Verification of Bisimulation Equivalence.
FORTE 1996: 279-294 |
1995 |
3 | | Teruo Higashino,
Akio Nakata,
Tatsuo Itoh,
Kenichi Taniguchi:
Verification of Liveness Property for Communicating FSM's with Conditional Transitions Depending on State Visiting Numbers.
FORTE 1995: 433-440 |
2 | EE | Akio Nakata,
Teruo Higashino,
Kenichi Taniguchi:
Protocol synthesis from timed and structured specifications.
ICNP 1995: 74- |
1993 |
1 | | Akio Nakata,
Teruo Higashino,
Kenichi Taniguchi:
LOTOS enhancement to specify time constraint among non-adjacent actions using first order logic.
FORTE 1993: 451-466 |