| 2008 |
|---|
| 8 | EE | Tomoya Kitani,
Nobuo Funabiki,
Hirozumi Yamaguchi,
Teruo Higashino:
Hierarchical Logical Topology in WDM Ring Networks with Limited ADMs.
Networking 2008: 326-337 |
| 7 | EE | Sho Kuroiwa,
Yoshihiro Murata,
Tomoya Kitani,
Keiichi Yasumoto,
Minoru Ito:
A Method for Assigning Men and Women with Good Affinity to Matchmaking Parties through Interactive Evolutionary Computation.
SEAL 2008: 645-655 |
| 6 | EE | Tomoya Kitani,
Takashi Shinkawa,
Naoki Shibata,
Keiichi Yasumoto,
Minoru Ito,
Teruo Higashino:
Efficient VANET-Based Traffic Information Sharing using Buses on Regular Routes.
VTC Spring 2008: 3031-3036 |
| 2007 |
|---|
| 5 | EE | Masataka Yonezu,
Nobuo Funabiki,
Tomoya Kitani,
Tokumi Yokohira,
Toru Nakanishi,
Teruo Higashino:
Proposal of a hierarchical heuristic algorithm for node assignment in bidirectional Manhattan street networks.
Systems and Computers in Japan 38(4): 74-83 (2007) |
| 2006 |
|---|
| 4 | EE | Takashi Shinkawa,
Takashi Terauchi,
Tomoya Kitani,
Naoki Shibata,
Keiichi Yasumoto,
Minoru Ito,
Teruo Higashino:
A Technique for Information Sharing using Inter-Vehicle Communication with Message Ferrying.
MDM 2006: 130 |
| 3 | EE | Hiroshi Nishikawa,
Shinya Yamamoto,
Morihiko Tamai,
Kouji Nishigaki,
Tomoya Kitani,
Naoki Shibata,
Keiichi Yasumoto,
Minoru Ito:
UbiREAL: Realistic Smartspace Simulator for Systematic Testing.
Ubicomp 2006: 459-476 |
| 2004 |
|---|
| 2 | EE | Tomoya Kitani,
Yoshifumi Takamoto,
Keiichi Yasumoto,
Akio Nakata,
Teruo Higashino:
A Flexible and High-Reliable HW/SW Co-Design Method for Real-Time Embedded Systems.
RTSS 2004: 437-446 |
| 2003 |
|---|
| 1 | EE | Tomoya Kitani,
Yoshifumi Takamoto,
Isao Naka,
Keiichi Yasumoto,
Akio Nakata,
Teruo Higashino:
Design and Implementation of Priority Queuing Mechanism on FPGA Using Concurrent Periodic EFSMs and Parametric Model Checking.
FPL 2003: 1145-1148 |
