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Yasuki Tanabe

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2005
4 Toshihiro Hanawa, Toshiya Minai, Yasuki Tanabe, Hideharu Amano: Implementation of ISIS-SimpleScalar. PDPTA 2005: 117-123
3EETakashi Midorikawa, Daisuke Shiraishi, Masayoshi Shigeno, Yasuki Tanabe, Toshihiro Hanawa, Hideharu Amano: The performance of SNAIL-2 (a SSS-MIN connected multiprocessor with cache coherent mechanism). Parallel Computing 31(3-4): 352-370 (2005)
2004
2 Masato Sumiyoshi, Takashi Midorikawa, Yasuki Tanabe, Hideharu Amano: Design and Evaluation of a Switch Architecture for Multistage Interconnection Network with Temporary Directory. ISCA PDCS 2004: 296-301
2003
1 Yasuki Tanabe, Takashi Midorikawa, Daisuke Shiraishi, Masayoshi Shigeno, Toshihiro Hanawa, Hideharu Amano: Performance Evaluation of 3-Dimensional MIN with Cache Consistency Maintenance Mechanism. PDPTA 2003: 1148-1154

Coauthor Index

1Hideharu Amano [1] [2] [3] [4]
2Toshihiro Hanawa [1] [3] [4]
3Takashi Midorikawa [1] [2] [3]
4Toshiya Minai [4]
5Masayoshi Shigeno [1] [3]
6Daisuke Shiraishi [1] [3]
7Masato Sumiyoshi [2]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)