| 2008 |
|---|
| 19 | EE | Roberto Giorgi,
Paolo Bennati:
Filtering drowsy instruction cache to achieve better efficiency.
SAC 2008: 1554-1555 |
| 18 | EE | Sandro Bartolini,
Irina Branovic,
Roberto Giorgi,
Enrico Martinelli:
Effects of Instruction-Set Extensions on an Embedded Processor: A Case Study on Elliptic Curve Cryptography over GF(2/sup m/).
IEEE Trans. Computers 57(5): 672-685 (2008) |
| 2007 |
|---|
| 17 | EE | Roberto Giorgi,
Zdravko Popovic,
Nikola Puzovic:
DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems.
SBAC-PAD 2007: 263-270 |
| 2006 |
|---|
| 16 | EE | Sandro Bartolini,
Roberto Giorgi:
Issues in Embedded Single-Chip Multicore Architectures.
J. Embedded Computing 2(2): 137-139 (2006) |
| 2005 |
|---|
| 15 | EE | Pierfrancesco Foglia,
Roberto Giorgi,
Cosimo Antonio Prete:
Reducing coherence overhead and boosting performance of high-end SMP multiprocessors running a DSS workload.
J. Parallel Distrib. Comput. 65(3): 289-306 (2005) |
| 2004 |
|---|
| 14 | EE | Sandro Bartolini,
Irina Branovic,
Roberto Giorgi,
Enrico Martinelli:
A Performance Evaluation of ARM ISA Extension for Elliptic Curve Cryptography over Binary Finite Fields.
SBAC-PAD 2004: 238-245 |
| 13 | EE | Pierfrancesco Foglia,
Roberto Giorgi,
Cosimo Antonio Prete:
Speeding-up multiprocessors running DBMS workloads through coherence protocols.
IJHPCN 1(1/2/3): 17-32 (2004) |
| 12 | EE | Irina Branovic,
Roberto Giorgi,
Enrico Martinelli:
A workload characterization of elliptic curve cryptography methods in embedded environments.
SIGARCH Computer Architecture News 32(3): 27-34 (2004) |
| 2002 |
|---|
| 11 | EE | Pierfrancesco Foglia,
Roberto Giorgi,
Cosimo Antonio Prete:
Boosting the Performance of Three-Tier Web Servers Deploying SMP Architecture.
NETWORKING Workshops 2002: 134-146 |
| 2001 |
|---|
| 10 | EE | Pierfrancesco Foglia,
Roberto Giorgi,
Cosimo Antonio Prete:
Evaluating Optimizing for Multiprocessors E-Commerce Server Running TPC-W Workload.
HICSS 2001 |
| 9 | | Krishna M. Kavi,
Joseph Arul,
Roberto Giorgi:
Performance Evaluation of a Non-Blocking Multithreaded Architecture for Embedded, Real-Time and DSP Applications.
ISCA PDCS 2001: 365-371 |
| 8 | EE | Krishna M. Kavi,
Roberto Giorgi,
Joseph Arul:
Scheduled Dataflow: Execution Paradigm, Architecture, and Performance Evaluation.
IEEE Trans. Computers 50(8): 834-846 (2001) |
| 7 | EE | Sandro Bartolini,
Roberto Giorgi,
Jelica Protic,
Cosimo Antonio Prete,
M. Valero:
Parallel architecture and compilation techniques: selection of workshop papers, guests' editors introduction.
SIGARCH Computer Architecture News 29(5): 9-12 (2001) |
| 2000 |
|---|
| 6 | EE | Pierfrancesco Foglia,
Roberto Giorgi,
Cosimo Antonio Prete:
Performance Analysis of Electronic Commerce Multiprocessor Server.
HICSS 2000 |
| 5 | EE | Krishna M. Kavi,
Joseph Arul,
Roberto Giorgi:
Execution and Cache Performance of the Scheduled Dataflow Architecture.
J. UCS 6(10): 948-967 (2000) |
| 1999 |
|---|
| 4 | | Pierfrancesco Foglia,
Roberto Giorgi,
Cosimo Antonio Prete:
Process Migration Effects on Memory Performance of Multiprocessor.
HiPC 1999: 133-142 |
| 3 | EE | Roberto Giorgi,
Cosimo Antonio Prete:
PSCR: A Coherence Protocol for Eliminating Passive Sharing in Shared-Bus Shared-Memory Multiprocessors.
IEEE Trans. Parallel Distrib. Syst. 10(7): 742-763 (1999) |
| 1997 |
|---|
| 2 | EE | Roberto Giorgi,
Cosimo Antonio Prete,
Gianpaolo Prina,
Luigi M. Ricciardi:
A Workload Generation Environment for Trace-Driven Simulation of Shared-Bus Multiprocessors.
HICSS (1) 1997: 266-275 |
| 1996 |
|---|
| 1 | EE | Roberto Giorgi,
Cosimo Antonio Prete,
Luigi M. Ricciardi,
Gianpaolo Prina:
A Hybrid Approach to Trace Generation for Performance Evaluation of Shared-Bus Multiprocessors.
EUROMICRO 1996: 207-214 |
