![]() | ![]() |
2005 | ||
---|---|---|
2 | EE | G. Boselli, C. Duvvury: Trends and challenges to ESD and Latch-up designs for nanometer CMOS technologies. Microelectronics Reliability 45(9-11): 1406-1414 (2005) |
2001 | ||
1 | EE | S. Voldman, W. Anderson, R. Ashton, M. Chaine, C. Duvvury, T. Maloney, E. Worley: A strategy for characterization and evaluation of ESD robustness of CMOS semiconductor technologies. Microelectronics Reliability 41(3): 335-348 (2001) |
1 | W. Anderson | [1] |
2 | R. Ashton | [1] |
3 | G. Boselli | [2] |
4 | M. Chaine | [1] |
5 | T. Maloney | [1] |
6 | S. Voldman | [1] |
7 | E. Worley | [1] |