| |
| 2007 | ||
|---|---|---|
| 3 | EE | Hsin-Chuan Chen, Jen-Shiun Chiang: A High-Performance Sequential MRU Cache Using Valid-Bit Assistant Search Algorithm. Journal of Circuits, Systems, and Computers 16(4): 613-626 (2007) |
| 2005 | ||
| 2 | EE | Hsin-Chuan Chen, Jen-Shiun Chiang: Low-Power Way-Predicting Cache Using Valid-Bit Pre-Decision for Parallel Architectures. AINA 2005: 203-206 |
| 2004 | ||
| 1 | EE | Hsin-Chuan Chen, Jen-Shiun Chiang: A low-jitter phase-interpolation DDS using dual-slope integration. IEICE Electronic Express 1(12): 333-338 (2004) |
| 1 | Jen-Shiun Chiang | [1] [2] [3] |